HD74CDC2509B driver equivalent, 3.3-v phase-lock loop clock driver.
*
*
*
*
* Meets “PC SDRAM registered DIMM design support document, Rev. 1.2” Phase-lock loop clock distribution for synchronous DRAM applications Exte.
External feedback (FBIN) pin is used to synchronize the outputs to the clock input No external RC network required Suppo.
Image gallery
Download